1. Field of Invention
The invention is related to the direction of access cycles to various buses in a multi-bus system.
2. Background Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386, 80486, or 80586 (Pentium.RTM.) microprocessor manufactured by Intel Corporation. The CPU is coupled to a host (local) bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-66 MHz;). The host bus generally includes 16, 32, or 64 data lines, a plurality of address lines, and various control lines. For present purposes the following signals on the host bus are important:
______________________________________ Signal Name Signal Description ______________________________________ HD[63:0] Host Bus Data Lines. HA[31:3] Host Bus Address Lines. BE[7:0]# Byte enables 7 through 0: Selects the active byte lanes on HD[63:0]. INTR Interrupt Request: INTR is driven to signal the processor that an interrupt request is pending and needs to be serviced. M/IO# Memory/Input-Output: M/IO# defines processor bus cycles along with D/C#, and W/R#. D/C# Data/Control: D/C# defines processor bus cycles along with M/I0# and W/R#. W/R# Write/Read: W/R# defines processor bus cycles along with M/I0# and D/C#. ADS# Address Strobe: The processor asserts ADS# to indicate that a new bus cycle is beginning BRDY# Burst Ready: BRDY# indicates that the system has responded in one of three ways: 1) Valid data has been placed on the processor data bus in a response to a read, 2) Processor write data has been accepted by the system, or 3) the system has responded to a special cycle. STPCLK# Stop Clock: this signal is connected to the STPCLK# input of the processor. It causes the processor to get into the STPGNT# state. ______________________________________
The typical IBM PC AT-compatible computer also includes a system bus, sometimes referred to as an I/O bus. Such a system bus is used to interface communications between a host CPU and a peripheral device, or communications between peripheral devices and host memory. The system bus is coupled to the host bus via certain interface circuitry. The system bus includes generally 8, 16, or 32 data lines, a plurality of address lines, as well as control/status lines. One of the most commonly used system buses is the industry standard architecture (ISA) bus. The ISA bus was adopted by several computer industry groups in the 1980's to create a standard to permit the development of compatible add-on cards in a reasonable and consistent fashion. The ISA bus operates at approximately 8 Mhz and includes 8 or 16 data lines, distinct address lines, as well as distinct control and command lines.
The various signals on the ISA bus are well specified and known in the industry. General information on the ISA bus can be found in Solari, "AT Bus Design" (San Diego, Annabooks, 1990), incorporated by reference herein. For present purposes, the following ISA signals are important:
______________________________________ Signal Name Signal Description ______________________________________ SA[23:0] 24 address lines. BALE Bus address latch enable line. BALE is an active high signal asserted to indicate when the SA address, AEN and SBHE# lines are valid. BALE remains asserted throughout ISA master and DMA cycles. SBHE# System byte high enable. When SBHE# is active, it indicates that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. AEN Address enable line. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. When active, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. SD[15:0] 16 data lines. MEMR# Read request lines to a memory resource on the ISA bus. MEMW# Write request lines to a memory resource on the ISA bus. IOR# Read request line to an I/O resource on the ISA bus. Also called IORC# or IORD#. IOW# Write request line to an I/O resource on the ISA bus. Also called IOWC# or IOWR#. M16# Memory chip select 16. Asserted by an addressed memory resource on the ISA bus if the resource can support a 16-bit memory access cycle. Also called MEMSC16#. I016# I/O chip select 16. Asserted by an addressed I/O resource on the ISA bus if the resource can support a 16-bit I/O access cycle. Also called IOCS16#. NOWS# Synchronous Ready line. Also sometimes called 0WS#, SRDY# or ENDXFR#. Activated by an addressed memory resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. If this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. Also sometimes called CHRDY. IRQ(15, 14, Interrupt request lines to 12:9, 7:3) interrupt controller for CPU. DMARQ (7:5, DMA Request lines from I/O 3:0) resource on ISA bus. DACK(7:5, DMA Acknowledge lines. 3:0) BCLK ISA bus clock signal. ______________________________________
Recently, efforts have been made to develop other bus protocols for PC AT-compatible computers with the goals of reducing the size of PC AT-compatible computers as well as continued industry standardization. These efforts have included the development of the PCI bus, which has been developed to establish a new industry standard for bus architectures, particularly those interfacing with high bandwidth functions. The PCI bus is described in detail in "PCI Local Bus Specification", Revision 2.1 (Portland, Oreg., PCI Special Interest Group, 1995), incorporated by reference herein. For present purposes, the following PCI signals are important:
______________________________________ Signal Name Signal Description ______________________________________ AD[31:0] PCI Address and Data: AD[31:0] are bidirectional address and data lines for the PCI bus. FRAME# Cycle Frame: FRAME# is driven the current bus master to indicate the beginning and duration of an access. FRAME# is asserted to indicate that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. IRDY# Initiator Ready: IRDY# indicates the initiating agent's (the bus master's) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on each clock that both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD[31:0]. During a read, it indicates the master is prepared to accept data. TRDY# Target Ready: TRDY# indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is asserted. During a read, TRDY# indicates that valid data is present on Ad[31:0]. during a write, it indicates the TRDY# is proper. DEVSEL# Device Select: When actively driven, DEVSEL# indicates the driving device has decoded its address as the target of the current access. STOP# Stop: STOP# indicates that the current target is requesting a master to stop the current transaction. PCICLK Master PCI clock. CLKRUN# Clock Run: CLKRUN# is an I/O sustained tristate signal used by the central resource (the host) to request permission to stop or slow the PCICLK. ______________________________________
Despite PCI bus development, because the PCI bus was designed primarily to support high-end peripherals (i.e., supporting speeds of up to 66 Mhz for 64-bit data), it is not as economical to manufacture low-end peripherals for the PCI-bus as it is for the older and slower ISA-bus. Thus both PCI-type devices and ISA-type devices are commonly produced and computer systems must be developed which have the interfaces to support both PCI-type and ISA-type devices.
Generally, in performing a read or write access to a system bus device, the host processor typically initiates an I/O access cycle by asserting M/IO#, W/R#, D/C#, and an I/O address. System interface circuitry recognizes the I/O signals generated by the host processor, performs the desired operation over the system bus, and if appropriate, returns results to the host processor over the host bus.
When the system bus is an ISA bus and when the interface circuitry receives an access cycle initiated by the host processor, the interface circuitry merely directs the cycle onto the ISA bus. The target devices on the ISA bus will decode the address asserted, and the appropriate device (the one addressed) will claim the cycle, and then perform a data transfer.
One drawback of this ISA device bus claiming scheme, however, is that ISA devices generally give no indication to the interface circuitry, or to any other device, that they are claiming particular cycles. The ISA device simply engages in the procedure to begin transmitting or receiving data.
The PCI bus attempts to solve the addressing problems experienced with ISA buses. With the PCI bus, during an initial configuration cycle, every device on the PCI bus is first assigned a specific address range which uniquely identifies the device. Further, all address lines (AD[31:0]) on the PCI bus are coupled to every PCI device, and each device performs its own address decoding. Finally, each device on the PCI bus asserts a DEVSEL# signal, which indicates when asserted that the device is claiming the cycle.
PCI 2.1 supports two styles of address decoding: positive and subtractive. Positive decoding occurs when a device is "looking" for accesses into the address range to which it has been assigned, and is generally faster than subtractive decoding. When a device "sees" its address on the bus, i.e., when signals are asserted on the address bus indicating an address in the device's address range, the device positively claims the cycle and asserts DEVSEL#, indicating to other PCI devices that it is claiming the cycle.
Subtractive decoding occurs when a device accepts accesses which are not accepted by any other device. Thus subtractive decoding can only be performed by one device on the PCI bus. In addition, subtractive decoding is generally slower than positive decoding since it effectively gives all other devices on the bus a "right of first refusal" on each access. If a device claims a cycle by subtractive decoding, it also asserts a DEVSEL# signal, indicating to other PCI devices that it "owns" the bus, i.e., that it claims the cycle. Further details regarding addressing and address decoding on the PCI bus can be found in PCI 2.1.
Because PCI and ISA as well as other types of system buses are common, many systems are built to support multiple bussing schemes. In such multi-bus systems, when the CPU or other device initiates an I/O access cycle, the interface circuitry must direct the cycle to the appropriate bus. This type of situation has most often been handled using the positive-subtractive decode scheme of the PCI bus. For instance, upon receiving a cycle, the interface circuitry first directs the cycle to the PCI bus, where it will be positively or subtractively decoded by PCI devices. If no PCI device, including the interface circuitry, positively claims the access cycle, the cycle is subtractively claimed by the interface circuitry. The interface circuitry is thus a PCI device and further acts as the single PCI subtractive decoder on the PCI bus. The interface circuitry then directs the subtractively claimed cycle to the local ISA bus. Thus, the local ISA bus receives the cycle by default.
This system of positive and subtractive decoding has tended to work well with free-standing PC systems. Notebook computers with docking stations, however, pose a more difficult problem. Notebook computers, or other mobile devices, when standing independently, typically have a similar bus structure to a desktop system, i.e., host processor, interface circuitry, ISA bus, PCI bus, etc., and will thus operate as described above. When a notebook system is docked, or placed in a docking station, however, a second ISA bus is usually linked to the notebook system. I/O cycles initiated from the host processor (on the notebook) must then be identified by the interface circuitry as destined for the ISA bus local to the notebook system (the "local ISA bus"), the PCI bus, or the remote ISA bus accessed through the docking station.
The presence of a remote ISA bus will raise several problems. First, remote ISA devices can claim the same address ranges as local ISA devices and therefore a bus conflict can result, particularly when both devices are trying to put data onto the bus for a read cycle. Second, the remote ISA devices, like their local ISA counterparts, still do not acknowledge that they are claiming a particular cycle. Therefore, if a cycle is directed to the remote ISA bus and the cycle is not claimed by a remote ISA device, the computer system may be significantly slowed.
The solution to these problems which is generally practiced is that for various more permanent local ISA resources (e.g., ROM, KBC, RTC) whose I/O addresses are known at manufacturing time, the known addresses are stored in registers in the interface circuitry. When a cycle directed to the PCI bus is ultimately destined for a local permanent ISA device address, the interface circuitry is programmed to positively claim the cycle when the cycle is on the PCI bus and then to direct the cycle to the local ISA bus. Otherwise the cycle is directed to the remote ISA bus. While this scenario aids in avoiding conflict with known local devices, it does not overcome the problematic situation where additional ISA devices (add-on cards) are added to the local ISA bus. Identifying which ISA bus a cycle should be directed to is usually a guessing game at best and can lead to bus conflict situations. Therefore, because conventionally there has not been a good way to determine when an ISA device is claiming a cycle, most designers minimize use of ISA devices.
Thus, it is desirable to develop a system which can recognize when a device on a second ISA bus claims a cycle, allowing bus conflicts to be minimized.